Name
Abstract | ||
|---|---|---|
By storing multibit per cell, multilevel cell (MLC) NAND flash memory achieves high storage capacity, but sacrificing data reliability. Error correction codes, such as Bose–Chaudhuri–Hocquenghem (BCH) codes, are widely used to ensure data reliability. However, high raw bit error rates induced by interference noises make BCH codes become insufficient to guarantee data reliability. Low-density parity-check (LDPC) codes are considered as the replacement due to the stronger error correction capability. Nevertheless, directly exploiting LDPC codes introduces a concern about decoding latency because of their iterative decoding in the soft decision process. To develop effective LDPC decoding algorithms, it is necessary to have a more profound understanding on flash failure patterns. This paper first observes the pair-bit errors (PBEs) characteristic of MLC NAND flash memory on a real field-programmable gate array testing platform, then proposes a PBE-aware LDPC (PAL) decoding scheme-based upon this observation, in which PBE provides the promotion information for LDPC decoding to reduce decoding latency. Simulation results show that the decoding latency can be reduced by up to 54%, compared with the conventional LDPC codes. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/TCAD.2018.2878132 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | Field | DocType |
Decoding,Interference,Reliability,Error correction codes,Iterative decoding,Testing | Nand flash memory,Computer science,Electronic engineering,Computer hardware,Ldpc decoding,Bit error rate | Journal |
Volume | Issue | ISSN |
38 | 12 | 0278-0070 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Meng Zhang | 1 | 16 | 5.23 |
| Fei Wu | 2 | 104 | 35.76 |
| Yajuan Du | 3 | 8 | 5.21 |
| Weihua Liu | 4 | 5 | 1.51 |
| Changsheng Xie | 5 | 32 | 9.93 |