Designing Coalescing Network-on-Chip for Efficient Memory Accesses of GPGPUs. - Citegraph

Paper Info

Title
Designing Coalescing Network-on-Chip for Efficient Memory Accesses of GPGPUs.

Year	DOI	Venue
2014	10.1007/978-3-662-44917-2_15	NPC
Field	DocType	Citations
Multithreading,Scheduling (computing),Computer science,Parallel computing,Network packet,Network on a chip,General-purpose computing on graphics processing units,Critical path method,Router,Memory controller	Conference	2
PageRank	References	Authors
0.37	14	8

Authors (8 rows)

Cited by (2 rows)

References (14 rows)

Name	Order	Citations	PageRank
Chien-Ting Chen	1	2	0.37
Yoshi Shih-Chieh Huang	2	31	2.73
Yuan-Ying Chang	3	24	3.03
Chiao-Yun Tu	4	2	0.37
Chung-Ta King	5	450	74.71
Tai-Yuan Wang	6	2	0.71
Janche Sang	7	66	13.03
Ming-Hua Li	8	2	0.37

1