Abstract | ||
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Emerging parallel applications re- quire a significant improvement in communication latency. Since the time required for transferring data between host memory and network interface (NI) takes up a large portion of overall communi- cation latency, the reduction of data transfer time is crucial for achieving low-latency communica- tion. In this paper, a new data transfer mechanism - called hereafter the DT, is proposed to reduce communication latency for latency demanding applications. The DT employs a cache coherence interface hardware to utilize an eager method for transferring data between the host and NI. Our simulation results show that the DT significantly reduces message latency up to 36 % compared to a Direct Memory Access (DMA) based approach. |
Year | Venue | Keywords |
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2006 | PDPTA | cache coherence,message.,user- level,eager method,low-latency,network pro- tocols,data transfer,direct memory access,network interface,network protocol,low latency |
Field | DocType | Citations |
Data transmission,Computer science,MESIF protocol,Parallel computing,MESI protocol,Network architecture,Computer network,Network traffic control,Distributed computing,Communications protocol,Write-once | Conference | 0 |
PageRank | References | Authors |
0.34 | 11 | 2 |
Name | Order | Citations | PageRank |
---|---|---|---|
Chul-ho Won | 1 | 42 | 13.41 |
Jong-Hoon Youn | 2 | 74 | 12.97 |