Title
Scheduling for Combining Traffic of On-Chip Trace Data in Embedded Multi-core Processor
Abstract
On-chip trace data contains run-time information of embedded multi-core processors for software debug. Trace data are transferred through special data path and output pins. Scheduling for combining the traffic of multi-source trace data is one of key issues that affect performance of the on-chip trace system. By analyzing features of trace traffic combination, a lazy scheduling algorithm based on the service threshold and the minimum service granularity is proposed. The queue length distribution is constrained by configurable service threshold of each queue, and switching overheads are reduced by lazy scheduling and configurable minimum service granularity. Two metrics of buffer utilizations on overflowing are presented to evaluate the efficacy of queue priority assignment. Simulation results show that the algorithm controls the overflow rate of each queue effectively and utilizes the buffer capacity according to the queues priority assigned sufficiently. The algorithm is realized in Verilog-HDL. Comparing with a leading method, the overflow rate is reduced 30% with additional 2,015um2in area.
Year
DOI
Venue
2007
10.1007/978-3-540-72685-2_7
ICESS
Keywords
Field
DocType
on-chip trace data,combining traffic,trace traffic combination,minimum service granularity,overflow rate,configurable service threshold,configurable minimum service granularity,multi-core processor,multi-source trace data,on-chip trace system,queue length distribution,trace data,multi core processor,scheduling algorithm,chip
Multilevel queue,Computer science,Scheduling (computing),Multilevel feedback queue,Queue,Parallel computing,Computer network,Real-time computing,Priority queue,Queue management system,Dynamic priority scheduling,Earliest deadline first scheduling
Conference
Volume
ISSN
Citations 
4523
0302-9743
0
PageRank 
References 
Authors
0.34
4
3
Name
Order
Citations
PageRank
Xiao Hu102.03
Pengyong Ma211.70
Shuming Chen313838.21