Paper Info
Title
A 3.3-V analog front-end chip for HomePNA applications
Abstract
In this paper, we designed the analog front-end chip for HomePNA (Home Phoneline Networking Alliance) physical layer applications. The chip mainly consists of the transmitter (Tx) path and receiver (Rx) path. The transmitter path includes the pulse generation block, Tx filter, programmable gain amplifier, and line driver. The receiver path includes the input buffer, automatic gain control amplifier, Rx filter, and slicing circuit with variable threshold level. The chip is fabricated in a 0.35-μm CMOS technology and consumes power dissipation of 150 mW at a 3.3-V supply voltage
Year
DOI
Venue
2001
10.1109/ISCAS.2001.922333
ISCAS (4)
Keywords
Field
DocType
cmos analogue integrated circuits,automatic gain control amplifier,0.35 micron,line driver,variable threshold slicing circuit,pulse generation block,power dissipation,transmitter,analog front-end chip,telephone equipment,programmable gain amplifier,home automation,receiver,physical layer,low-power electronics,150 mw,filter,cmos technology,home phoneline networking alliance,homepna,3.3 v,input buffer,gain control,automatic gain control,chip,transmitters,low power electronics,voltage
HomePNA,Analog front-end,Computer science,Chip,CMOS,Electronic engineering,Line driver,Automatic gain control,Programmable-gain amplifier,Electrical engineering,Amplifier
Conference
Volume
ISBN
Citations 
4
0-7803-6685-9
1
PageRank 
References 
Authors
0.38
0
6
Name
Order
Citations
PageRank
Jaeyoung Shin152.13
Joong-Ho Choi24210.78
Jinup Lim3122.70
Sungwon Noh431.11
Namil Baek510.38
Jong-hyeong Lee610.38