Paper Info
Title
Scan chain design for test time reduction in core-based ICs
Abstract
The size of the test vector set forms a significant factor in the overall production costs of ICs, as it defines the test applicationtime and the required pin memory size of the test equipment. Large core-based ICs often require a very large test vector setfor a high test coverage. This paper deals with the design of scan chains as transport mechanism for test patterns from IC pinsto embedded cores and vice versa. The number of pins available to accommodate scan test is given, as well as the number ofscan test patterns and scannable flip flops of each core. We present and analyze three scan chain architectures for core-basedICs, which aim at a minimum test vector set size. We give experimental results of the three architectures for an industrial IC.Furthermore we analyze the test time consequences of reusing cores with fixed internal scan chains in multiple ICs with varyingdesign parameters.
Year
DOI
Venue
1998
10.1109/TEST.1998.743185
ITC
Keywords
Field
DocType
test equipment,large test vector setfor,test time consequence,test applicationtime,test time reduction,number ofscan test pattern,minimum test vector set,test vector set,high test coverage,large core-based ics,test pattern,chain design,design for test,job shop scheduling,design for testability,production,test coverage
Code coverage,Design for testing,Boundary scan,Automatic test pattern generation,Test vector,Automatic test equipment,Computer science,Scan chain,Electronic engineering,Real-time computing,Test compression,Embedded system
Conference
ISSN
ISBN
Citations 
1089-3539
0-7803-5093-6
116
PageRank 
References 
Authors
14.75
5
2
Search Limit
100116
Name
Order
Citations
PageRank
Joep Aerts113417.32
Erik Jan Marinissen22053170.58