Name
Abstract | ||
|---|---|---|
A planar floating-gate NAND technology has previously realized a 0.87Gb/mm2 memory density using 3b/cell [1] and achieved a minimum feature size for 16nm [2]. However, the development of planar NAND flash is expected to reach the scaling limit in a few technology generations. To break though this limit, a significant shift to 3D NAND flash has begun and several types of 3D memory cell structures have been proposed and discussed [3–5]. Recently a 3D V-NAND technology achieved 1.86Gb/mm2 using charge-trap cells and 3b/cell [6]. This paper presents a 3b/cell NAND flash memory utilizing a 3D floating gate (FG) technology that achieves 4.29Gb/mm2. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/ISSCC.2016.7417947 | 2016 IEEE International Solid-State Circuits Conference (ISSCC) |
Keywords | Field | DocType |
3D-floating-gate NAND flash memory,memory density,3D memory cell,charge-trap cells,3D floating gate technology,size 16 nm | Nand flash memory,Logic gate,Scaling limit,Computer science,Electronic engineering,CMOS,NAND gate,Non-volatile memory,Planar,Science, technology and society,Electrical engineering | Conference |
ISBN | Citations | PageRank |
978-1-4673-9466-6 | 9 | 1.36 |
References | Authors | |
2 | 61 | |