Name
Abstract | ||
|---|---|---|
DRAM disturbance errors are increasingly a concern to computer system reliability and security. There have been a number of designs to detect and prevent them; however, there lacks any design that guarantees 100 percent detection (no false negative) with a small and fixed hardware cost. This paper presents such a design based on a novel idea called disturbance bin counter (DBC). Each DBC is a comp... |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/LCA.2019.2897299 | IEEE Computer Architecture Letters |
Keywords | Field | DocType |
Random access memory,Upper bound,Microprocessors,Computer architecture,Indexes,Transistors,Hash functions | Row,Dram,Bin,Computer science,Upper and lower bounds,Parallel computing,dBc,Critical path method,Computer hardware,Spec#,Memory controller | Journal |
Volume | Issue | ISSN |
18 | 1 | 1556-6056 |
Citations | PageRank | References |
2 | 0.40 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yicheng Wang | 1 | 22 | 8.06 |
| Liu Yang | 2 | 10 | 2.89 |
| Peiyun Wu | 3 | 2 | 0.40 |
| Zhao Zhang | 4 | 78 | 7.12 |