Paper Info
Title
Design and linearity analysis of a M-2M DAC for very low supply voltage
Abstract
This work presents the design of a 6 bits M-2M ladder Digital-to-Analog Converter (DAC) proper for operation under supply voltages of 200 mV or lower. Since the MOS transistors are operating in the subthreshold region under such low supply, the mismatch analysis was done using an all-region continuous MOSFET model. The performance of the circuit is evaluated through simulations and the trade-offs between linearity, supply voltage and sampling rate are investigated in the paper. It is proposed that a 6 bits M-2M DAC operating under 200 mV and with sampling rate of 5.1MS/s is feasible using a commercial 130 nm process and standard transistors.
Year
DOI
Venue
2015
10.1109/ICECS.2015.7440304
2015 IEEE International Conference on Electronics, Circuits, and Systems (ICECS)
Keywords
Field
DocType
linearity analysis,M-2M DAC,very low supply voltage,M-2M ladder digital-analog converter,all-region continuous MOSFET model,voltage 200 mV,size 130 nm
EKV MOSFET Model,Integral nonlinearity,Computer science,Sampling (signal processing),Linearity,Voltage,Control engineering,Electronic engineering,Subthreshold conduction,Transistor,Electrical engineering
Conference
Citations 
PageRank 
References 
0
0.34
6
Authors
3
Name
Order
Citations
PageRank
Israel Sperotto100.34
hamilton klimach27120.07
sergio bampi3496102.12