Name
Abstract | ||
|---|---|---|
Structured quasi-cyclic low-density parity-check (QC-LDPC) code is a part of many emerging wireless communication standards, such as WiMAX, WiFi and WPAN. This paper presents a high parallel decoder architecture for the QC-LDPC codes and the corresponding decoder ASIC for WiMAX system. Through utilizing the proposed fully parallel layered scheduling architecture, the decoder chip saves 22.2% memory bits and takes 24~48 clock cycles per iteration for different code rates. It occupies 3.36 mm2 in SMIC 65nm CMOS, and realizes 1Gbps (1056Mbps) throughput at 1.2V, 110MHz and 10 iterations with the power 115mW and power efficiency 10.9pJ/bit/iteration. The energy/bit/iteration reduces 63.6% in normalized comparison with the state-of-art publication. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ASSCC.2011.6123576 | A-SSCC |
Keywords | Field | DocType |
cmos integrated circuits,wimax,application specific integrated circuits,cyclic codes,parity check codes,scheduling,qc-ldpc decoder asic,smic cmos process,wpan,wifi,wimax system,bit rate 1 gbit/s,frequency 110 mhz,high parallel decoder architecture,parallel layered scheduling architecture,power 115 mw,size 65 nm,structured quasicyclic low-density parity-check code,voltage 1.2 v,wireless communication standards,registers,power efficiency,decoding,low density parity check,ldpc code,wireless communication,chip | Wireless,Low-density parity-check code,Computer science,Chip,Electronic engineering,WiMAX,Application-specific integrated circuit,CMOS,Real-time computing,Throughput,Decoding methods,Embedded system | Conference |
ISBN | Citations | PageRank |
978-1-4577-1784-0 | 7 | 0.69 |
References | Authors | |
3 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xiao Peng | 1 | 47 | 6.69 |
| Zhixiang Chen | 2 | 20 | 4.17 |
| Xiongxin Zhao | 3 | 20 | 4.44 |
| Dajiang Zhou | 4 | 355 | 50.25 |
| Satoshi Goto | 5 | 14 | 4.21 |