Name
Abstract | ||
|---|---|---|
We present a novel version of the FPGA-based Universal Link for LVDS (low-voltage differential signaling) communications that reduces the power consumption by sending the information only when a new data is input. In the a regular LVDS protocol, 4 wires are required for a full duplex communication. The aim of the Universal Link is to reduce the amount of wires in the network by sending data from N signal through a single connection. These new approach reduces the number of bits transmitted to 84% of the original system, when N = 2, and up to 23% for N > 130. Also, the sampling frequency is considerable reduced. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/LASCAS.2016.7451065 | 2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS) |
Keywords | Field | DocType |
Universal Link,LVDS,spacewire | Differential signaling,Computer science,Sampling (signal processing),Field-programmable gate array,Electronic engineering,Power demand,Time–frequency analysis,Power consumption,Duplex (telecommunications) | Conference |
ISSN | Citations | PageRank |
2330-9954 | 0 | 0.34 |
References | Authors | |
0 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Luis Sanchez | 1 | 0 | 0.34 |
| Giancarlo Patiño | 2 | 0 | 0.34 |
| V. Murray | 3 | 197 | 16.47 |
| James Lyke | 4 | 15 | 4.15 |