Name
Abstract | ||
|---|---|---|
Modern field-programmable gate array (FPGA) devices often contain complex clocking architectures to achieve high-performance and flexible clock networks. The physical structure of these clock networks, however, are pre-manufactured, unadjustable, and with only limited routing resources. Most conventional FPGA placement algorithms rarely consider clock feasibility, and therefore lead to clock routing failures. Some recent works adopt simplified clock routing models (e.g., the bounding box model) to force clock legality during placement, which, however, can often overestimate clock routing demands and results in unnecessary placement quality degradation. To address these limitations, in this paper, we propose a generic FPGA placement framework that can simultaneously optimize placement quality and ensure clock feasibility by explicit clock tree construction. We demonstrate the effectiveness and efficiency of the proposed approach using the ISPD 2017 Clock-Aware Placement Contest benchmark suite. Compared with other state-of-the-art clock legalization algorithms, the proposed approach can achieve the best routed wirelength with competitive runtime.
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Year | DOI | Venue |
|---|---|---|
2019 | 10.1145/3289602.3293897 | FPGA |
Field | DocType | ISBN |
Suite,Computer science,Parallel computing,Clock tree,Field-programmable gate array,Gate array,Physical design,Clock routing,Physical structure,Embedded system,Minimum bounding box | Conference | 978-1-4503-6137-8 |
Citations | PageRank | References |
0 | 0.34 | 21 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wuxi Li | 1 | 36 | 6.03 |
| Mehrdad E. Dehkordi | 2 | 0 | 0.34 |
| Stephen Yang | 3 | 26 | 2.67 |
| David Z. Pan | 4 | 2653 | 237.64 |