Name
Abstract | ||
|---|---|---|
The simultaneous use of FPGAs by multiple tenants has recently been shown to potentially expose sensitive information without the victim's knowledge. For example, neighboring long wires in SRAM-based FPGAs have been shown to allow for clandestine data exfiltration. In this work, we explore distinct characteristics of this signal crosstalk that could be used to enhance or prevent information leakage. First, we develop a mechanism to characterize the crosstalk coupling that exists between neighboring wires at the femtosecond scale. Second, we show that it is possible to reverse engineer channel layouts by determining which pairs of routing resources/links in the channel exhibit coupling to each other even if this information is not provided by the FPGA vendor. To fully characterize these effects, we examine long wire coupling on different types of wires across three devices implemented in different technology nodes from 65 to 20 nm. We experimentally demonstrate that information leakage is apparent for all three FPGA families.
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Year | DOI | Venue |
|---|---|---|
2019 | 10.1145/3289602.3293923 | FPGA |
Keywords | Field | DocType |
FPGA, side channel, crosstalk | Coupling,Information leakage,Leakage (electronics),Computer science,Parallel computing,Reverse engineering,Communication channel,Field-programmable gate array,Electronic engineering,Static random-access memory,Side channel attack | Conference |
ISBN | Citations | PageRank |
978-1-4503-6137-8 | 4 | 0.42 |
References | Authors | |
7 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| George Provelengios | 1 | 22 | 4.38 |
| Chethan Ramesh | 2 | 4 | 0.42 |
| Shivukumar B. Patil | 3 | 17 | 2.25 |
| Ken Eguro | 4 | 195 | 15.97 |
| R. Tessier | 5 | 235 | 26.75 |
| Daniel E. Holcomb | 6 | 462 | 31.63 |