Name
Abstract | ||
|---|---|---|
Due to inherent error resiliency, many high performance multimedia applications can be approximated by multi-layer perceptrons (MLPs), with little quality loss. An MLP accelerator can be designed to improve the power efficiency of multimedia systems. However, previous MLP accelerators’ fixed computational pattern lowers the performance when the MLP topology varies for different applications. In this paper, we propose a scheduling framework to guide mapping MLPs onto limited hardware resources. The scheduling framework adjusts the computational patterns for various MLP topologies, obtaining 30% higher performance than the conventional scheduling. We implement a reconfigurable neural architecture (RNA) to support different patterns in the framework and further improve the performance and efficiency. RNA achieves a speedup of
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on the approximable part, whole application speedup of
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and energy savings of
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, with little quality loss on the benchmarks. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/TCSVT.2018.2812781 | IEEE Transactions on Circuits and Systems for Video Technology |
Keywords | Field | DocType |
Hardware,Computer architecture,Neurons,RNA,Processor scheduling,Multimedia computing,Computational modeling | Electrical efficiency,Architecture,Computer science,Scheduling (computing),Network topology,Processor scheduling,Multimedia,Perceptron,Speedup | Journal |
Volume | Issue | ISSN |
29 | 3 | 1051-8215 |
Citations | PageRank | References |
1 | 0.37 | 3 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Fengbin Tu | 1 | 71 | 8.62 |
| shouyi yin | 2 | 579 | 99.95 |
| Peng Ouyang | 3 | 129 | 19.36 |
| leibo liu | 4 | 816 | 116.95 |
| Shaojun Wei | 5 | 555 | 102.32 |