Name
Abstract | ||
|---|---|---|
The ever-increasing demand for higher bandwidth continues to fuel the need for faster and more power-efficient IOs, with the next generation high-speed serial links expected to reach data rates higher than 112Gb/s using PAM-4 signaling [1–3]. While PAM-4 spectral efficiency is better than that of NRZ, it is less tolerant of residual ISI and noise. As a consequence, a driver with high bandwidth and large output amplitude is required. This paper presents a 64Gbaud PAM-4 TX with a fully reconfigurable 3-tap FFE, which achieves a power efficiency of 1.3pJ/b in PAM-4 mode and 2.7pJ/b in NRZ mode for a differential output swing of $1\mathrm{V}_{ppd}$. A feature of the FFE construction is the use of fully re-assignable FFE segments among the 3 taps, which allows a reduced number of segments for lower capacitance and higher driver bandwidth. To minimize power consumption, a quarter-rate clocking architecture is adopted with a tailless 4:1 multiplexer, which also acts as a pre-driver to a tailless CML output driver. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/ISSCC.2019.8662479 | 2019 IEEE International Solid- State Circuits Conference - (ISSCC) |
DocType | ISBN | Citations |
Conference | 978-1-5386-8531-0 | 4 |
PageRank | References | Authors |
0.52 | 0 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zeynep Toprak Deniz | 1 | 90 | 11.02 |
| jonathan e proesel | 2 | 5 | 1.68 |
| John F. Bulzacchelli | 3 | 281 | 42.62 |
| Herschel A. Ainspan | 4 | 157 | 25.23 |
| Timothy O. Dickson | 5 | 141 | 22.86 |
| Michael P. Beakes | 6 | 215 | 21.36 |
| M. Meghelli | 7 | 54 | 13.87 |