Name
Abstract | ||
|---|---|---|
Three-dimensional integrated circuits (3-D ICs) are considered to meet the performance needs of future ICs. The core components of 3-D ICs are through-silicon vias (TSVs), which should pass appropriate prebond and post-bond tests in 3-D IC fabrication processes. The test inputs must be injected into the TSVs, and the test results must be extracted. This paper proposes a new test result extraction scheme [fast result extraction by selective shift-out (FRESH)] for prebond and post-bond TSV testing. With additional hardware, the proposed scheme remarkably reduces the TSV test time. FRESH avoids unnecessary test result extraction when the number of faulty TSVs in the TSV set is 0 or exceeds the number of TSV redundancies in the set. These early fault analyses are executed in the checkers of TSV groups. The experimental results show that the proposed scheme can reduce the result extraction time in practical environments. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/TCAD.2016.2578883 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | Field | DocType |
Through-silicon vias,Maintenance engineering,Three-dimensional displays,Circuit faults,Testing,Hardware | Computer science,Semiconductor device fabrication,Electronic engineering,Integrated circuit,Maintenance engineering,Reliability engineering,Embedded system | Journal |
Volume | Issue | ISSN |
36 | 2 | 0278-0070 |
Citations | PageRank | References |
2 | 0.39 | 15 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jaeseok Park | 1 | 19 | 6.05 |
| Hyunyul Lim | 2 | 20 | 4.46 |
| Sungho Kang | 3 | 12 | 6.64 |