Name
Abstract | ||
|---|---|---|
For high data rate, new mechanisms such as Block Ack and frame aggregation are currently being discussed in IEEE 802.11e and IEEE 802.11n, respectively. These mechanisms need a short response time in each MPDU processing. In this paper, we propose an efficient design of CCMP for IEEE 802.11i to support these new MAC mechanisms. The proposed design adopts the mode toggling approach, in which MIC calculation and data encryption are sequentially performed for each 128 bits of the packet in only one AESCCM core. In our design, the response time is reduced to a short constant period, which takes only 44 clock cycles. In addition, we can reduce hardware complexity and power consumption, because our design uses one AES-CCM core and obtains the reasonable data throughput and response time at even low clock frequency. We have implemented the proposed design, which is targeted to Altera Stratix FPGA device. As a result of the experiments, the CCMP features 285 Mbps data throughput and 0.88 μs . response time at 50 MHz frequency. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1007/11734727_28 | ICISC |
Keywords | Field | DocType |
aes-ccm core,response time,efficient design,robust security network,reasonable data throughput,high data rate,aesccm core,short response time,mbps data throughput,ccmp feature,proposed design | Stratix,Computer science,CCMP,Response time,Field-programmable gate array,Frame aggregation,Throughput,Cycles per instruction,Clock rate,Embedded system | Conference |
Volume | ISSN | ISBN |
3935 | 0302-9743 | 3-540-33354-1 |
Citations | PageRank | References |
5 | 0.66 | 5 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Duhyun Bae | 1 | 9 | 1.84 |
| Gwanyeon Kim | 2 | 52 | 6.29 |
| Jiho Kim | 3 | 57 | 15.00 |
| Sehyun Park | 4 | 269 | 36.03 |
| Oh-young Song | 5 | 271 | 26.40 |