Name
Abstract | ||
|---|---|---|
A 1.8-V 12-bit fully differential self-calibrating SAR ADC is presented in a standard 0.18-mu m CMOS technology. To improve the SNDR and achieve a low core area, it adapts a capacitive self-calibrating method. The way to estimate the calibration range is discussed. Based on a minimizing capacitance principle, a novel comparator is proposed to enhance speed and save power. At the speed of 6 MS/s, the ADC achieves 11.3 ENOB by Spectre simulation, with estimated comparator offset of 30mV and unit capacitor mismatch of 4% sigma. It consumes 839 mu W for the analog part. |
Year | Venue | Field |
|---|---|---|
2015 | PROCEEDINGS OF 2015 IEEE 11TH INTERNATIONAL CONFERENCE ON ASIC (ASICON) | Capacitor,Comparator,Capacitance,Computer science,12-bit,Effective number of bits,Electronic engineering,CMOS,Capacitive sensing,Successive approximation ADC |
DocType | ISSN | Citations |
Conference | 2162-7541 | 0 |
PageRank | References | Authors |
0.34 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chenxi Deng | 1 | 0 | 1.01 |
| Long Zhao | 2 | 0 | 4.06 |
| Hui Zheng | 3 | 19 | 5.74 |
| Yu-Hua Cheng | 4 | 2 | 5.85 |