Paper Info
Title
Accelerating object detection via a visual-feature-directed search cascade: algorithm and field programmable gate array implementation
Abstract
Object detection is a major step in several computer vision applications and a requirement for most smart camera systems. Recent advances in hardware acceleration for real-time object detection feature extensive use of reconfigurable hardware [field programmable gate arrays (FPGAs)], and relevant research has produced quite fascinating results, in both the accuracy of the detection algorithms as well as the performance in terms of frames per second (fps) for use in embedded smart camera systems. Detecting objects in images, however, is a daunting task and often involves hardware-inefficient steps, both in terms of the datapath design and in terms of input/output and memory access patterns. We present how a visual-feature-directed search cascade composed of motion detection, depth computation, and edge detection, can have a significant impact in reducing the data that needs to be examined by the classification engine for the presence of an object of interest. Experimental results on a Spartan 6 FPGA platform for face detection indicate data search reduction of up to 95%, which results in the system being able to process up to 50 1024 x 768 pixels images per second with a significantly reduced number of false positives. (C) 2016 SPIE and IS&T
Year
DOI
Venue
2016
10.1117/1.JEI.25.4.041013
JOURNAL OF ELECTRONIC IMAGING
Keywords
Field
DocType
object detection,depth extraction,edge detection,motion detection,field programmable gate array,hardware architecture
Computer vision,Object detection,Motion detection,Computer science,Edge detection,Smart camera,Artificial intelligence,Hardware acceleration,Face detection,Hardware architecture,Reconfigurable computing
Journal
Volume
Issue
ISSN
25
4
1017-9909
Citations 
PageRank 
References 
1
0.35
0
Authors
2
Name
Order
Citations
PageRank
Christos Kyrkou110214.05
Theocharis Theocharides220526.83