Name
Abstract | ||
|---|---|---|
A conditional-boosting flip-flop is proposed for ultralow-voltage application where the supply voltage is scaled down to the near-threshold region. The proposed flip-flop adopts voltage boosting to provide low latency with reduced performance variability in the near-threshold voltage region. It also adopts conditional capture to minimize the switching power consumption by eliminating redundant boosting operations. Experimental results in a 65-nm CMOS process indicated that the proposed flip-flop provided up to 72% lower latency with 75% less performance variability due to process variation, and up to 67% improved energy-delay product at 25% switching activity compared with conventional precharged differential flip-flops. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/TVLSI.2016.2595627 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | Field | DocType |
Boosting,Pulse generation,Capacitors,Niobium,Threshold voltage,Latches,Switches | Capacitor,Latency (engineering),Computer science,Voltage,Real-time computing,Electronic engineering,Process variation,Boosting (machine learning),Latency (engineering),Flip-flop,Threshold voltage | Journal |
Volume | Issue | ISSN |
25 | 2 | 1063-8210 |
Citations | PageRank | References |
0 | 0.34 | 6 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jihoon Park | 1 | 143 | 27.61 |
| Hyun-Seung Seo | 2 | 0 | 0.68 |
| Bai-Sun Kong | 3 | 153 | 31.93 |