Paper Info
Title
Bridging the FPGA programmability-portability Gap via automatic OpenCL code generation and tuning
Abstract
Programming FPGAs has been an arduous task that requires extensive knowledge of hardware design languages (HDLs), such as Verilog or VHDL, and low-level hardware details. With OpenCL support for FPGAs, the design, prototyping and implementation of an FPGA is increasingly moving towards a much higher level of abstraction, when compared to the intrinsically low-level nature of HDLs. On the other hand, in the context of traditional (i.e., CPU) software development, OpenCL is still considered to be low-level and complex because the programmer needs to manually expose parallelism in the code. In this work, we present our approach to enhancing FPGA programmability via GLAF, a visual programming framework, to automatically generate synthesizable OpenCL code with an array of FPGA-specific optimizations. We find that our tool facilitates the development process and produces functionally correct and well-performing code on the FPGA for our molecular modeling, gene sequence search, and filtering algorithms.
Year
DOI
Venue
2016
10.1109/ASAP.2016.7760796
2016 IEEE 27th International Conference on Application-specific Systems, Architectures and Processors (ASAP)
Keywords
Field
DocType
FPGA,programmability-portability gap,OpenCL,hardware design languages,Verilog,VHDL,CPU,software development,GLAF,visual programming,molecular modeling,gene sequence search,filtering algorithms
Computer architecture,Programmer,Computer science,Parallel computing,Field-programmable gate array,Visual programming language,Code generation,Software portability,Verilog,VHDL,Software development,Embedded system
Conference
ISSN
ISBN
Citations 
1063-6862
978-1-5090-1504-7
0
PageRank 
References 
Authors
0.34
3
3
Name
Order
Citations
PageRank
Konstantinos Krommydas1595.82
Ruchira Sasanka200.34
Wu-chun Feng32812232.50