Name
Abstract | ||
|---|---|---|
Detailed knowledge of a circuit's timing is essential for performance optimization, timing closure, and generation of test patterns to detect small-delay defects. When an input transition is applied to the circuit's inputs, the resulting delay is not only determined by the propagation path, but also influenced by the power-supply noise. We introduce a path-sensitization procedure which precisely controls the switching activity in the circuit region surrounding the path. The procedure can maximize or minimize switching activity, or set it to a user-specified value. We study the accuracy-vs.-efficiency trade-offs for a hierarchy of timing models, from coarse zero-delay assumption to a waveform-accurate approach with sub-cycle resolution. For the first time, we present a MaxSAT formulation which guarantees maximization or minimization of switching activity, stemming from transitions and from glitches, simultaneously with path sensitization. We validate the quality of the generated test patterns using a mixed-mode IR-drop-aware timing simulator. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/ATS.2016.63 | 2016 IEEE 25th Asian Test Symposium (ATS) |
Keywords | Field | DocType |
ATPG,low power,sensitizable path,formal methods,optimization | Maximum satisfiability problem,Automatic test pattern generation,Glitch,Logic gate,Computer science,Algorithm,Electronic engineering,Real-time computing,Static timing analysis,Minification,Maximization,Timing closure | Conference |
ISSN | ISBN | Citations |
1081-7735 | 978-1-5090-3810-7 | 0 |
PageRank | References | Authors |
0.34 | 21 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Matthias Sauer | 1 | 195 | 20.02 |
| Jie Jiang | 2 | 19 | 1.76 |
| sven reimer | 3 | 45 | 4.48 |
| Kohei Miyase | 4 | 562 | 38.71 |
| Xiaoqing Wen | 5 | 790 | 77.12 |
| B. Becker | 6 | 191 | 21.44 |
| Ilia Polian | 7 | 889 | 78.66 |