Paper Info
Title
Split Wisely: When Work Partitioning Is Energy-Optimal On Heterogeneous Hardware
Abstract
Heterogeneous System-on-Chip (SoC) processors are increasingly gaining traction in the High Performance Computing (HPC) community as alternate building blocks for future exascale systems. Key issues relating to their promise of energy efficiency include i) absolute performance, ii) finding an energy-optimal balance in the use of different on-chip devices and iii) understanding the performance-energy trade-offs while using different on-chip devices.In this paper we explore these issues through an energy usage model designed to predict the existence of an energy-optimal work partition between different processing elements on heterogeneous systems for any application. We validate our model by measuring performance and energy consumption of matrix multiplication on the NVIDIA Tegra K1 and X1 systems. An environment for monitoring and responding to energy usage is also outlined and used to perform high resolution measurements. Comparisons are drawn with conventional HPC systems housing Intel Xeon CPUs alongside NVIDIA GPUs.
Year
DOI
Venue
2016
10.1109/HPCC-SmartCity-DSS.2016.189
PROCEEDINGS OF 2016 IEEE 18TH INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING AND COMMUNICATIONS; IEEE 14TH INTERNATIONAL CONFERENCE ON SMART CITY; IEEE 2ND INTERNATIONAL CONFERENCE ON DATA SCIENCE AND SYSTEMS (HPCC/SMARTCITY/DSS)
Keywords
Field
DocType
Energy usage model, SoC, NVIDIA, Tegra X1, Tegra K1, K20, K80, Load balancing, Energy efficiency, Intel, Haswell, Sandy bridge, uCurrent, Power Measurement
System on a chip,Supercomputer,Computer science,Efficient energy use,Xeon,Computer hardware,Matrix multiplication,Energy consumption,Usage model,Distributed computing,Embedded system
Conference
Citations 
PageRank 
References 
0
0.34
0
Authors
5
Name
Order
Citations
PageRank
Gaurav Mitra1494.29
Andrew Haigh200.34
Anish Varghese3131.31
Luke Angove400.34
Alistair P. Rendell520934.55