Name
Title | ||
|---|---|---|
Secure cryptographic hardware implementation issues for high-performance applications |
Abstract | ||
|---|---|---|
In this paper the effect of high-performance techniques for high speed applications in secure cryptographic implementations is studied. The use of dual pre charge logic styles with fine-grained pipelining with an overlapping three-phase clock scheme is studied, also including a correct distribution of the clock signal in the cryptographic implementation. To make this study, four different implementations of the Sbox-9 of the Kasumi algorithm have been implemented using an 90nm TSMC technology. Simulation-based DPA attacks have been carried out, showing how the proper synchronization of data signals gives better results in terms of power consumption and operating frequency, but affects negatively the security against side channel attacks, decreasing the number of input patterns needed to disclosure the secret key. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/PATMOS.2016.7833429 | 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) |
Keywords | Field | DocType |
VLSI design of cryptographic circuits,side-channel attacks,pipeline,differential CMOS digital circuits,power consumption,substitution box,high performance,correlation power analysis | Clock signal,Pipeline (computing),Synchronization,Cryptographic protocol,Computer science,Cryptography,Real-time computing,Cryptographic primitive,Electronic engineering,Side channel attack,KASUMI,Embedded system | Conference |
ISSN | ISBN | Citations |
2474-5456 | 978-1-5090-0734-9 | 0 |
PageRank | References | Authors |
0.34 | 10 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Erica Tena | 1 | 18 | 4.64 |
| Antonio J. Acosta | 2 | 93 | 16.97 |
| J. Núñez | 3 | 1 | 2.74 |