Name
Title | ||
|---|---|---|
Automatic ReRAM SPICE Model Generation From Empirical Data for Fast ReRAM-Circuit Coevaluation. |
Abstract | ||
|---|---|---|
This paper presents an automatic resistive random access memory (ReRAM) SPICE model generator, which enables fast ReRAM circuit evaluation with standard SPICE. Our model generator automatically produces SPICE models of ReRAM devices and selectors from the measured I-V data to reduce too much time consumption in manual model development for ReRAM devices and simulation of the target ReRAM circuits.... |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/TVLSI.2017.2655730 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | Field | DocType |
Data models,SPICE,Integrated circuit modeling,Resistance,Current measurement,Resistive RAM,Predictive models | Data modeling,Computer science,Spice,Electronic engineering,Electronic circuit,Computer hardware,Resistive random-access memory | Journal |
Volume | Issue | ISSN |
25 | 6 | 1063-8210 |
Citations | PageRank | References |
1 | 0.39 | 2 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| JaeHyun Seo | 1 | 1 | 0.39 |
| Sangheon Lee | 2 | 5 | 1.31 |
| Kwangmin Kim | 3 | 7 | 4.28 |
| sooeun lee | 4 | 9 | 3.11 |
| Hyunsang Hwang | 5 | 49 | 6.60 |
| Byungsub Kim | 6 | 165 | 37.71 |