Name
Title | ||
|---|---|---|
The Design and Implementation of a Latency-Aware Packet Classification for OpenFlow Protocol based on FPGA |
Abstract | ||
|---|---|---|
Packet classification has been recognized as one of the most significant functions in contemporary network infrastructures. Furthermore, a number of modern applications such as IoTs contain very strict constraints on the latency of network transmissions. This paper presents the design and implementation of a novel packet classification based on FPGA architecture. The proposed design contains a Latency Compression Scheme (LCS) to achieve the low-latency packet processing. Furthermore, this structure supports 12-tuple fields for the modern Internet traffics. The experimental results show that the proposed packet classification scheme reduces the delay of packet processing by 2.18× compared to the state-of-the-art works.
|
Year | DOI | Venue |
|---|---|---|
2018 | 10.1145/3301326.3301368 | Proceedings of the 2018 VII International Conference on Network, Communication and Computing |
Keywords | Field | DocType |
FPGA, Latency-Aware, OpenFlow, Packet classification | Latency (engineering),Computer science,Computer network,Field-programmable gate array,OpenFlow,Packet processing,Fpga architecture,Packet classification,The Internet | Conference |
ISBN | Citations | PageRank |
978-1-4503-6553-6 | 2 | 0.36 |
References | Authors | |
8 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yu-Kai Chiu | 1 | 6 | 4.24 |
| Shanq-Jang Ruan | 2 | 375 | 55.44 |
| Chung-An Shen | 3 | 86 | 12.61 |
| Chun-Chi Hung | 4 | 2 | 0.70 |