Name
Abstract | ||
|---|---|---|
This paper disproves the worst read scenario of a ReRAM crossbar array. If the previously believed worst read scenario is not the worst one, the read margin evaluated based on the scenario can be incorrect. We explored for read scenario worse than the previously believed worst scenario by wisely sampling scenarios and iteratively searching for the worse one. In experiment, our algorithm successful... |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/TVLSI.2017.2710140 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | Field | DocType |
Resistance,Leakage currents,Arrays,Sensors,Very large scale integration,Reliability,Algorithm design and analysis | Algorithm design,Computer science,Parallel computing,Real-time computing,Sampling (statistics),Very-large-scale integration,Crossbar array,Resistive random-access memory | Journal |
Volume | Issue | ISSN |
25 | 9 | 1063-8210 |
Citations | PageRank | References |
0 | 0.34 | 4 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yelim Youn | 1 | 0 | 0.68 |
| Kwangmin Kim | 2 | 7 | 4.28 |
| Jae-yoon Sim | 3 | 508 | 83.58 |
| Hong-june Park | 4 | 465 | 72.93 |
| Byungsub Kim | 5 | 165 | 37.71 |