Paper Info
Title
Address-free memory access based on program syntax correlation of loads and stores
Abstract
An increasing cache latency in next-generation processors incurs profound performance impacts in spite of advanced out-of-order execution techniques. One way to circumvent this cache latency problem is to predict load values at the onset of pipeline execution by exploiting either the load value locality or the address correlation of stores and loads. In this paper, we describe a new load value speculation mechanism based on the program syntax correlation of stores and loads. We establish a symbolic cache (SC), which is accessed in early pipeline stages to achieve a zero-cycle load. Instead of using memory addresses, the SC is accessed by the encoding bits of base register ID plus the displacement directly from the instruction code. Performance evaluations using SPEC95 and SPEC2000 integer programs on SimpleScalar simulation tools show that the SC achieves higher prediction accuracy in comparison with other load value speculation methods, especially when hardware resources are limited.
Year
DOI
Venue
2003
10.1109/TVLSI.2003.812315
IEEE Trans. VLSI Syst.
Keywords
Field
DocType
program syntax correlation,address correlation,load value speculation method,symbolic cache,cache latency,new load value speculation,advanced out-of-order execution technique,load value,cache latency problem,zero-cycle load,load value locality,address-free memory access,pipelines,out of order execution,out of order,encoding,integer programming,registers,predictive models,accuracy,hardware
Instruction set,Cache,CPU cache,Computer science,Latency (engineering),Real-time computing,Electronic engineering,Integer programming,Memory address,Out-of-order execution,Parallel computing,Encoding (memory),Embedded system
Journal
Volume
Issue
ISSN
11
3
1063-8210
Citations 
PageRank 
References 
0
0.34
22
Authors
4
Name
Order
Citations
PageRank
Peng Lu112617.62
Jih-Kwon Peir224834.53
Qianrong Ma300.34
Konrad K. Lai460448.45