Name
Abstract | ||
|---|---|---|
Thermal and energy consumption constitute a major problem in 3D NoC (Network on Chip) implementation. A considerable part of the energy consumed by an MPSoC is dissipated by the interconnect itself. Moreover, latency and routing complexity could introduce an unacceptable hindrance to the NoCs performances if conventional energy reduction techniques such as VFS (Voltage and Frequency Scaling) are used. We introduce a novel low-radix router based 3D NoC architecture that reduces both energy (≃ 26%) consumption and the interconnects area ≃ 40%) without causing a considerable performance loss (8.31% latency, 14.68% throughput for 48 nodes) compared to 4×4×3 3D Mesh network. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/IINTEC.2017.8325926 | 2017 International Conference on Internet of Things, Embedded Systems and Communications (IINTEC) |
Keywords | DocType | ISBN |
Network on Chip,3D NoC,Topology,Architecture,Low Radix,Energy,Area | Conference | 978-1-5386-2114-1 |
Citations | PageRank | References |
0 | 0.34 | 7 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Nejib Mediouni | 1 | 0 | 1.35 |
| Salem Hasnaoui | 2 | 1 | 5.44 |