Name
Abstract | ||
|---|---|---|
An improved BIJM (Built-in jitter measurement) circuit is presented in this paper, which is consisted of three improvement points. Firstly, multi-phase sampling technology improves the sampling efficiency based on the specially designed multi-phase clock generation circuit. Secondly, the median-edge alignment is used as the new jitter extraction method, which is taking the place of the mean-edge alignment. This method can filter low-frequency noise component to extract the cycle-to-cycle jitter. Thirdly, single-edge accumulation data processing method accumulates one edge in each cycle, blocking the correlation of adjacent sampling location, which can improve measurement accuracy and save the area overhead. The proposed jitter measurement circuit is designed at SMIC 40 nm CMOS process, and the circuit occupies a total silicon area of 9108 um(2). Post-layout simulation results show the measurement error is only 0.94%. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1587/elex.15.20180124 | IEICE ELECTRONICS EXPRESS |
Keywords | Field | DocType |
jitter, multi-phase undersampling, mean-edge alignment, single-edge accumulation | Computer science,Undersampling,Electronic engineering,Jitter | Journal |
Volume | Issue | ISSN |
15 | 8 | 1349-2543 |
Citations | PageRank | References |
0 | 0.34 | 5 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zhikuang Cai | 1 | 3 | 5.54 |
| Haobo Xu | 2 | 13 | 3.04 |
| Jian Xiao | 3 | 0 | 0.34 |
| Jun Yang | 4 | 147 | 36.54 |