Title
On-chip communication for neuro-glia networks.
Abstract
Hardware has become more prone to faults as a result of geometric scaling, wear-out and faults caused during the manufacturing process, therefore, the reliability of hardware is reliant on the need to continually adapt to faults. A computational model of biological self-repair in the brain, derived from observing the role of astrocytes (a glial cell found in the mammalian brain), has captured self...
Year
DOI
Venue
2018
10.1049/iet-cdt.2017.0187
IET Computers & Digital Techniques
Keywords
Field
DocType
integrated circuit interconnections,neural chips
Synapse,Computer science,Real-time computing,Implementation,Computational model,Interconnection,Artificial neural network,Ring network,Manufacturing process,Distributed computing,Scalability
Journal
Volume
Issue
ISSN
12
4
1751-8601
Citations 
PageRank 
References 
0
0.34
0
Authors
5
Name
Order
Citations
PageRank
George Martin100.68
Jim Harkin232536.82
Liam Mcdaid327030.48
John J. Wade41028.91
Junxiu Liu512523.91