Name
Title | ||
|---|---|---|
FASST: A high performance scalable rule table hardware architecture for software defined networks. |
Abstract | ||
|---|---|---|
In this paper, a new hardware architecture FASST, which can provide high performance in packet classification for SDN Rule Tables, is proposed. FASST achieves high throughput at very low packet latency using a TCAM-based parallel cache, temporal locality in the network and FPGA hardware parallelism. FASST is implemented and evaluated on Altera Stratix-V FPGA and 200 M packets/s throughput is verified functionally. FASST achieves a significantly lower average packet latency by exploiting the strong temporal locality of computer networks. |
Year | Venue | Keywords |
|---|---|---|
2018 | Signal Processing and Communications Applications Conference | Software Defined Network (SDN),packet classification,TCAM,Bit Vector,FPGA |
Field | DocType | ISSN |
Computer vision,Stratix,Computer architecture,Locality of reference,Computer science,Cache,Network packet,Field-programmable gate array,Artificial intelligence,Throughput,Hardware architecture,Scalability | Conference | 2165-0608 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Goksan Eral | 1 | 0 | 0.34 |
| Ece Guran Schmidt | 2 | 146 | 16.27 |