Name
Title | ||
|---|---|---|
Suitability of recent hardware accelerators (DSPs, FPGAs, and GPUs) for computer vision and image processing algorithms. |
Abstract | ||
|---|---|---|
Computer vision and image processing algorithms form essential components of many industrial, medical, commercial, and research-related applications. Modern imaging systems provide high resolution images at high frame rates, and are often required to perform complex computations to process image data. However, in many applications rapid processing is required, or it is important to minimise delays for analysis results. In these applications, central processing units (CPUs) are inadequate, as they cannot perform the calculations with sufficient speed. To reduce the computation time, algorithms can be implemented in hardware accelerators such as digital signal processors (DSPs), field-programmable gate arrays (FPGAs), and graphics processing units (GPUs). However, the selection of a suitable hardware accelerator for a specific application is challenging. Numerous families of DSPs, FPGAs, and GPUs are available, and the technical differences between various hardware accelerators make comparisons difficult. It is also important to know what speed can be achieved using a specific hardware accelerator for a particular algorithm, as the choice of hardware accelerator may depend on both the algorithm and the application. The technical details of hardware accelerators and their performance have been discussed in previous publications. However, there are limitations in many of these presentations, including: inadequate technical details to enable selection of a suitable hardware accelerator; comparisons of hardware accelerators at two different technological levels; and discussion of old technologies. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1016/j.image.2018.07.007 | Signal Processing: Image Communication |
Keywords | Field | DocType |
Review,Computer vision,Image processing,Digital signal processor (DSP),Field programmable gate array (FPGA),Graphics processing unit (GPU) | Graphics,Computer science,Digital signal processor,Algorithm,Field-programmable gate array,Chip,Frame rate,Hardware acceleration,Computer vision and image processing,Computer hardware,Computation | Journal |
Volume | ISSN | Citations |
68 | 0923-5965 | 5 |
PageRank | References | Authors |
0.74 | 44 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Amir HajiRassouliha | 1 | 11 | 4.85 |
| Andrew J. Taberner | 2 | 28 | 10.59 |
| Martyn P. Nash | 3 | 133 | 23.64 |
| Poul M. F. Nielsen | 4 | 328 | 29.20 |