Name
Abstract | ||
|---|---|---|
This work presents a CMOS analog multiplier architecture for application as the synapse in analog cellular neural networks. The circuit comprises two voltage-mode inputs and a current-mode output. Simulated performance features obtained from a circuit design in CMOS 130 nm technology include: +100 mV input voltage range, 23 µW static power, −32 dB maximum total harmonic distortion and −3 dB bandwidth of 51.2 kHz. The active area totalizes only 40 µm
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. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/LASCAS.2019.8667594 | 2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS) |
Keywords | Field | DocType |
Computer architecture,Synapses,Logic gates,MOSFET,Semiconductor device modeling,CMOS technology | Logic gate,Total harmonic distortion,Analog multiplier,Semiconductor device modeling,Computer science,Voltage,Circuit design,CMOS,Electronic engineering,Cellular neural network | Conference |
ISSN | ISBN | Citations |
2330-9954 | 978-1-7281-0453-9 | 0 |
PageRank | References | Authors |
0.34 | 0 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Antônio José Sobrinho de Sousa | 1 | 0 | 0.68 |
| Fernando Martins Cardoso | 2 | 0 | 1.01 |
| Kelvin Kéfren Carvalho Feitosa Nunes | 3 | 0 | 0.34 |
| fabian souza de andrade | 4 | 2 | 2.85 |
| Gabriele Costa Gonçalves | 5 | 0 | 1.01 |
| edson pinto santana | 6 | 4 | 4.10 |
| Ana Isabela Araujo Cunha | 7 | 3 | 3.90 |