Name
Abstract | ||
|---|---|---|
Fabrication-less integrated circuit (IC) design houses outsource fabrication to third-party foundries to reduce cost of manufacturing. The outsourcing of IC fabrication, beyond our expectation, raises concerns regarding intellectual property (IP) piracy and theft by rogue elements in the third-party foundries. Obfuscation techniques have been proposed to increase resistance to reverse engineering, IP recovery, IP theft, and piracy. However, prior work on obfuscation for IP protection has primarily applied to the gate level or the layout level. As a result, it can significantly impact the performance of the original design in addition to requiring redesign of standard cells.
In this article, we propose a high-level synthesis and analysis (HLSA)-based obfuscation approach for IP protection. The proposed method is based on split manufacturing. Additional dummy units and MUXes can be added to further obfuscate the design. The proposed technique aligns with the standard-cell-based design methodologies and does not significantly impact the performance of the original design. Our experimental results confirm that the proposed approach can provide high levels of IC obfuscation with moderate area cost.
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Year | DOI | Venue |
|---|---|---|
2019 | 10.1145/3289156 | JETC |
Keywords | Field | DocType |
IP piracy, RT-level, high-level synthesis and analysis, obfuscation, split manufacturing | Computer science,Semiconductor device fabrication,Reverse engineering,Outsourcing,Electronic engineering,Register-transfer level,Intellectual property,Ip piracy,Obfuscation,Integrated circuit,Embedded system | Journal |
Volume | Issue | ISSN |
15 | 1 | 1550-4832 |
Citations | PageRank | References |
1 | 0.35 | 20 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xiaotong Cui | 1 | 26 | 4.86 |
| Jeff Jun Zhang | 2 | 12 | 1.90 |
| Kaijie Wu | 3 | 724 | 56.35 |
| Siddharth Garg | 4 | 675 | 55.14 |
| Ramesh Karri | 5 | 2968 | 224.90 |