Title
A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains
Abstract
Correctly operating digital SoC domains at their target frequencies require the addition of supply voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm{ dd}}$ </tex-math></inline-formula> ) guardbands to account for supply droop events and temperature variation. These guardbands degrade processor energy efficiency, especially in low-voltage sensor and IoT applications due to increased delay sensitivity to temperature and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm{ dd}}$ </tex-math></inline-formula> variation. In this paper, we present an all-digital unified clock and power (UniCaP-SC) architecture that combines switched-capacitor (SC)-based voltage control and clock frequency regulation into a single loop to significantly reduce required <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm{ dd}}$ </tex-math></inline-formula> guardbands. A UniCaP-SC test chip consisting of a near-threshold voltage (NTV) ARM Cortex-M0 processor was fabricated in 65-nm CMOS. The fully integrated system enables all-digital construction, aggressive <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm{ dd}}$ </tex-math></inline-formula> margin reduction, and continuous <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm{ dd}}$ </tex-math></inline-formula> scalability using SC-based voltage converters while no additional decoupling capacitance (decap). Test-chip measurements demonstrate a 16% <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm{ dd}}$ </tex-math></inline-formula> reduction corresponding to a 94% <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm{ dd}}$ </tex-math></inline-formula> margin recovery or an equivalent <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.2\times $ </tex-math></inline-formula> increase in the operating clock frequency ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{\mathrm{ clk}}$ </tex-math></inline-formula> ).
Year
DOI
Venue
2019
10.1109/JSSC.2018.2888866
IEEE Journal of Solid-State Circuits
Keywords
Field
DocType
Clocks,Voltage control,Phase locked loops,Regulators,Delays,Scalability
Phase-locked loop,Topology,Capacitance,Computer science,Control theory,Voltage,Switched capacitor,CMOS,Low voltage,Clock rate,Voltage droop
Journal
Volume
Issue
ISSN
54
4
0018-9200
Citations 
PageRank 
References 
2
0.36
0
Authors
8
Name
Order
Citations
PageRank
Fahim U. Rahman162.81
Sung Kim2727.41
Naveen John331.06
Roshan Kumar420.70
Xi Li510829.17
Pamula, V.R.6256.43
Keith A. Bowman7977138.36
Visvesh S. Sathe818529.53