Title | ||
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A Unified Clock and Switched-Capacitor-Based Power Delivery Architecture for Variation Tolerance in Low-Voltage SoC Domains |
Abstract | ||
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Correctly operating digital SoC domains at their target frequencies require the addition of supply voltage (
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) guardbands to account for supply droop events and temperature variation. These guardbands degrade processor energy efficiency, especially in low-voltage sensor and IoT applications due to increased delay sensitivity to temperature and
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variation. In this paper, we present an all-digital unified clock and power (UniCaP-SC) architecture that combines switched-capacitor (SC)-based voltage control and clock frequency regulation into a single loop to significantly reduce required
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guardbands. A UniCaP-SC test chip consisting of a near-threshold voltage (NTV) ARM Cortex-M0 processor was fabricated in 65-nm CMOS. The fully integrated system enables all-digital construction, aggressive
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margin reduction, and continuous
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scalability using SC-based voltage converters while no additional decoupling capacitance (decap). Test-chip measurements demonstrate a 16%
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reduction corresponding to a 94%
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margin recovery or an equivalent
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increase in the operating clock frequency (
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). |
Year | DOI | Venue |
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2019 | 10.1109/JSSC.2018.2888866 | IEEE Journal of Solid-State Circuits |
Keywords | Field | DocType |
Clocks,Voltage control,Phase locked loops,Regulators,Delays,Scalability | Phase-locked loop,Topology,Capacitance,Computer science,Control theory,Voltage,Switched capacitor,CMOS,Low voltage,Clock rate,Voltage droop | Journal |
Volume | Issue | ISSN |
54 | 4 | 0018-9200 |
Citations | PageRank | References |
2 | 0.36 | 0 |
Authors | ||
8 |
Name | Order | Citations | PageRank |
---|---|---|---|
Fahim U. Rahman | 1 | 6 | 2.81 |
Sung Kim | 2 | 72 | 7.41 |
Naveen John | 3 | 3 | 1.06 |
Roshan Kumar | 4 | 2 | 0.70 |
Xi Li | 5 | 108 | 29.17 |
Pamula, V.R. | 6 | 25 | 6.43 |
Keith A. Bowman | 7 | 977 | 138.36 |
Visvesh S. Sathe | 8 | 185 | 29.53 |