Name
Abstract | ||
|---|---|---|
Image processing algorithms are dominating contemporary digital systems due to their importance and adoption by a large number of application domains. Despite their significance, their computational requirements often limit their usage, especially in deeply embedded designs. Heterogeneous computing systems offer a promising solution for this performance gap, leading to their ever increasing utilization by designers. This work targets the acceleration of an image registration pipeline on a System-on-Chip (SoC) including both general purpose and re-configurable computing elements. The evaluation of our proposed HW/SW co-designed image registration application on a state-of-the-art FPGA based SoC showcases its ability to outperform software designs leading to orders of performance speedup (up to 67x) against embedded CPUs.
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Year | DOI | Venue |
|---|---|---|
2019 | 10.1145/3312614.3312636 | COINS |
Keywords | Field | DocType |
Affine Transformation, Correlation Similarity Metric, Downhill Simplex, Image Registration, Zynq | Computer science,Symmetric multiprocessor system,Field-programmable gate array,Software,Acceleration,Hardware acceleration,Digital image processing,Computer engineering,Image registration,Speedup | Conference |
ISBN | Citations | PageRank |
978-1-4503-6640-3 | 0 | 0.34 |
References | Authors | |
0 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ioannis Stratakos | 1 | 0 | 1.01 |
| Dimitrios Gourounas | 2 | 0 | 0.68 |
| Vasileios Tsoutsouras | 3 | 35 | 8.88 |
| Theodore L. Economopoulos | 4 | 0 | 0.34 |
| George K. Matsopoulos | 5 | 107 | 22.99 |
| Dimitrios Soudris | 6 | 89 | 26.17 |