Title
PSION - Combining Logical Topology and Physical Layout Optimization for Wavelength-Routed ONoCs.
Abstract
Optical Networks-on-Chip (ONoCs) are a promising solution for high-performance multi-core integration with better latency and bandwidth than traditional Electrical NoCs. Wavelength-routed ONoCs (WRONoCs) offer yet additional performance guarantees. However, WRONoC design presents new EDA challenges which have not yet been fully addressed. So far, most topology analysis is abstract, i.e., overlooks layout concerns, while for layout the tools available perform Place & Route (P&R) but no topology optimization. Thus, a need arises for a novel optimization method combining both aspects of WRONoC design. In this paper such a method, PSION, is laid out. When compared to the state-of-the-art design procedure, results show a 1.8x reduction in maximum optical insertion loss.
Year
DOI
Venue
2019
10.1145/3299902.3309747
ISPD
Keywords
Field
DocType
optical networks-on-chip, silicon photonics, physical layout, design optimization, placement & routing
Logical topology,Mathematical optimization,Computer science,Latency (engineering),Electronic engineering,Bandwidth (signal processing),Topology optimization,Silicon photonics,Insertion loss,Wavelength
Conference
ISBN
Citations 
PageRank 
978-1-4503-6253-5
5
0.48
References 
Authors
0
5
Name
Order
Citations
PageRank
Alexandre Truppel191.60
Tsun-Ming Tseng27411.12
Davide Bertozzi3165399.83
José Carlos Alves4245.39
Ulf Schlichtmann510921.56