Name
Abstract | ||
|---|---|---|
Compared to pipelined analog-to-digital converters (ADCs), pipelined- successive approximation register (SAR) ADCs have been actively explored for better energy efficiency in recent years. Nonetheless, the pipelined-SAR architecture inherently limits the sampling speed of the ADC due to the slow operation of the first SAR ADC, which becomes an increasingly important limitation with the recent expansion of high-speed applications. In this paper, we introduce our new design of a pipelined-SAR ADC to enable faster speed. New loop-unrolled architecture with the split capacitor is used for the first SAR ADC to improve the speed. A resistive open-loop multiplying digital-to-analog converter with a new calibration scheme is designed to reduce the power consumption at high speed. As a result, the 65-nm design can achieve 300-MS/s sampling rate with a single channel. It is among the fastest pipelined-SAR ADC design so far. The peak signal-to-noise-and-distortion ratio is 63.6 dB with a 10-MHz input. It consumes 12.5-mW power from a 1.2-V supply to achieve a power efficiency of 34 fJ/conversion-step. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/JSSC.2018.2886327 | IEEE Journal of Solid-State Circuits |
Keywords | Field | DocType |
Capacitors,Delays,Latches,Calibration,Pipelines,Switches,Power demand | Electrical efficiency,Flight dynamics (spacecraft),Capacitor,Computer science,Sampling (signal processing),12-bit,Communication channel,Converters,Electronic engineering,Successive approximation ADC | Journal |
Volume | Issue | ISSN |
54 | 5 | 0018-9200 |
Citations | PageRank | References |
2 | 0.46 | 0 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chao Wu | 1 | 15 | 8.86 |
| George Jie Yuan | 2 | 174 | 22.14 |