Name
Title | ||
|---|---|---|
Circuit-Size Reduction for Parallel Chien Search using Minimal Polynomial Degree Reduction |
Abstract | ||
|---|---|---|
The circuit of parallel Chien search is the largest in the decoder for long Bose-Chaudhuri-Hocquenghem (BCH) codes with strong correction capability. It can be decomposed into two functional blocks. One is the shift block which stores and transforms an error locator polynomial. The rest consists of substitution circuits which substitute finite field values into the polynomial to find its roots, which indicate error locations. For circuit-size reduction of the substitution, an error locator polynomial is divided by a product of minimal polynomials. If there are common roots between a dividend and divisor, the remainder inherits the common roots. Hence, error locations can be found by testing the remainder with the lower degree than that of the error locator polynomial. Our new architecture needs additional operations, such as the division. However, for 122-error-correcting BCH codes over GF(2
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">15</sup>
), our new architecture can reduce the circuit size of the 16-parallel Chien search by 17% compared with an optimized conventional architecture. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/ISCAS.2019.8702075 | 2019 IEEE International Symposium on Circuits and Systems (ISCAS) |
Keywords | Field | DocType |
Computer architecture,Registers,Decoding,Transforms,Flash memories,Matrices,Wires | Chien search,Finite field,Polynomial,Control theory,Computer science,Arithmetic,Remainder,BCH code,Minimal polynomial (linear algebra),Decoding methods,Divisor | Conference |
ISSN | ISBN | Citations |
0271-4302 | 978-1-7281-0397-6 | 0 |
PageRank | References | Authors |
0.34 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Naoaki Kokubun | 1 | 0 | 0.68 |
| Akira Yamaga | 2 | 0 | 0.68 |
| Hironori Uchikawa | 3 | 38 | 5.56 |
| Daiki Watanabe | 4 | 0 | 0.34 |