Name
Title | ||
|---|---|---|
A 0.14-3.5 GHz All Digital PLL with improved fast frequency-lock and a novel TDC-based self-calibration capability |
Abstract | ||
|---|---|---|
An AD-PLL with a self-calibrated hierarchical Time to Digital Converter (TDC) is proposed to attain a wide range of operation and a phase error monitor to reduce the process lock. To cover a wide range of frequency with improved spectral purity, two digitally controlled oscillators are proposed. An LC-tank oscillator with a tunable active inductor is used to reach the on-GHz band with a fine tuning resolution, while the sub-GHz is covered by an interpolated ring DCO. The proposed ADPLL is designed using a 90 nm TSMC CMOS process. The operational frequency range of the proposed circuit varies from 140 MHz to 3.52 GHz. The ADPLL achieves a fast settling time of less than 5 μs. By consuming 13.4 mW, the frequency synthesizer achieves -105 dBc/Hz far-off phase noise and -55 dBc fractional spur. |
Year | DOI | Venue |
|---|---|---|
2018 | 10.1109/ICM.2018.8704046 | 2018 30th International Conference on Microelectronics (ICM) |
Keywords | Field | DocType |
Oscillators,Microelectronics,Active inductors,Tuning,Capacitance,Monitoring,Switches | Spectral purity,Phase-locked loop,Settling time,Computer science,Phase noise,Inductor,Electronic engineering,Frequency synthesizer,dBc,Time-to-digital converter | Conference |
ISBN | Citations | PageRank |
978-1-5386-8167-1 | 0 | 0.34 |
References | Authors | |
0 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sehmi Saad | 1 | 0 | 0.34 |
| Mhiri, M. | 2 | 6 | 4.40 |
| Aymen Ben Hammadi | 3 | 3 | 0.87 |
| Kamel Besbes | 4 | 44 | 15.41 |