Name
Abstract | ||
|---|---|---|
Accurate evaluation of Ultra Low Power Systems on Chip (ULP SoC) is a huge challenge for designers and developers. In embedded applications, especially for Internet of Things end-node devices, ULP SoCs have to interact with their environment, but modelling a complete SoC and the peripheral components, their interaction and low-power policies, can be very complex in terms of developments and benchmarking. In order to cope with this challenge, an approach is to implement the desired system on FPGA with a monitoring infrastructure dedicated to fast and accurate evaluation. This paper presents a reconfigurable prototyping platform used for SoC architecture exploration and real-time application evaluation. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/SAS.2019.8706095 | 2019 IEEE Sensors Applications Symposium (SAS) |
Keywords | Field | DocType |
Monitoring,Field programmable gate arrays,Random access memory,Tools,Microcontrollers,Estimation,Registers | Sensor node,Architecture,Computer science,Internet of Things,Embedded applications,Field-programmable gate array,Electric power system,Real-time computing,Microcontroller,Benchmarking,Embedded system | Conference |
ISBN | Citations | PageRank |
978-1-5386-7713-1 | 3 | 0.46 |
References | Authors | |
0 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Guillaume Patrigeon | 1 | 4 | 2.52 |
| Paul Leloup | 2 | 3 | 0.46 |
| P. Benoit | 3 | 74 | 12.39 |
| Lionel Torres | 4 | 346 | 53.92 |