Name
Abstract | ||
|---|---|---|
This paper describes a SHA3 hash processor that is interfaced with Cortex-M0 to be used as an IP. The SHA3 hash processor was designed with a round-iterative structure of 1600-bit data-path, and it supports four different message digest sizes of 512, 384, 256, and 224 bits depending on the hash function used. The SHA3 processor interfaced with Cortex-M0 was verified by FPGA implementation. It was estimated to have a throughput of 5 Gbps at the maximum clock frequency of 289 MHz, and it occupied 1,692 slices of Virtex5 FPGA device. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.23919/ELINFOCOM.2019.8706419 | 2019 International Conference on Electronics, Information, and Communication (ICEIC) |
Keywords | DocType | ISSN |
Field programmable gate arrays,Hardware,Hash functions,NIST,Throughput,Software,Registers | Conference | 2377-8431 |
ISBN | Citations | PageRank |
978-89-950044-4-9 | 1 | 0.39 |
References | Authors | |
0 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Dong Seong Kim | 1 | 866 | 93.34 |
| Sang Hyun Lee | 2 | 206 | 33.61 |
| Kyung-Wook Shin | 3 | 1 | 0.39 |