Title
A fault-tolerant and congestion-aware architecture for wireless networks-on-chip
Abstract
The combination of traditional wired links for regular transmissions and express wireless paths for long distance communications is a promising solution to prevent multi-hop network delays. In wireless network-on-chip technology, wireless-equipped routers are more error-prone than the conventional ones not only because of their implementation complexities but also due to their relatively high utilization. In this paper, a new topology is presented to enhance the network reliability, and then a novel routing algorithm is proposed to tolerate both intermittent and permanent faults on wireless hubs. In the proposed approach, once a wireless hub becomes faulty, the best alternative adjustment hub will be indicated and all the packets that have high average hop-count are routed through this alternative hub. In comparison with the state-of-the-art works, the proposed approach shows significant improvements in terms of robustness, congestion management, and resilience.
Year
DOI
Venue
2019
10.1007/s11276-019-01962-3
Wireless Networks
Keywords
Field
DocType
Network-on-chip, Hybrid wireless network-on-chip, Many-core system-on-chip, Reliability, Robustness, Congestion control management
Psychological resilience,Wireless network,Wireless,Computer science,Network packet,Computer network,Network on a chip,Robustness (computer science),Fault tolerance,Reliability (computer networking),Distributed computing
Journal
Volume
Issue
ISSN
25.0
6
1572-8196
Citations 
PageRank 
References 
0
0.34
25
Authors
4
Name
Order
Citations
PageRank
Seyed Hassan Mortazavi100.34
r akbar232.75
Farshad Safaei39519.37
Amin Rezaei4688.33