Name
Abstract | ||
|---|---|---|
The design of a heterogeneous network-on-chip (NoC) based H.264 video decoder is proposed. A thorough investigation using a system simulator developed as the combination of a cycle accurate NoC simulator together with complete implementations of all the video decoder modules is presented. The target hardware platform is a multicore system-on-chip, where the cores were designed for specific functions that correspond to the modules of the video decoder. Because such cores have different sizes and aspect ratios, a heterogeneous NoC is employed to facilitate the communication between modules. This is different from the reference case of a homogeneous NoC based hardware platform, where all cores are general purpose processors with the same area and where the NoC is a regular mesh NoC. The investigation looks at the impact of core sizes and floorplan for a given technology node as well as at the performance variation across several technology nodes.
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Year | DOI | Venue |
|---|---|---|
2019 | 10.1145/3299874.3318013 | Proceedings of the 2019 on Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
h.264 video decoder, heterogeneous network-on-chip, homogeneous network-on-chip | Aspect ratio (image),Computer architecture,General purpose,Computer science,Homogeneous,Real-time computing,Implementation,Heterogeneous network,Multi-core processor,Video decoder,Floorplan | Conference |
ISSN | ISBN | Citations |
1066-1395 | 978-1-4503-6252-8 | 0 |
PageRank | References | Authors |
0.34 | 0 | 2 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Milad Ghorbani Moghaddam | 1 | 9 | 4.70 |
| Cristinel Ababei | 2 | 8 | 3.93 |