Name
Abstract | ||
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As the capacity of FPGA increases, FPGA placers that adopt Simulated Annealing (SA) algorithm take more and more runtime. To solve this problem, this paper presents HCAS, a Hybrid algorithm Combining Analytical method and SA. There are three modifications in HCAS: (1) In global placement, faster and better result is realized by modified analytical algorithm. (2) In detailed placement, proper tradeoff is made between quality and runtime through improvement of SA. (3) Optimization workload of timing and wirelength is reasonably assigned between global and detailed placement according to algorithm features. HCAS is implemented in the newest VPR. Compared to VPR placer, it obtains a speedup of 11.1x, with 3% shorter wirelength and 5% smaller critical path delay. Compared to other analytical-based hybrid placers, HCAS achieves greater speedup and enhancement of placement quality is similar or better.
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Year | DOI | Venue |
|---|---|---|
2019 | 10.1145/3299874.3318035 | Proceedings of the 2019 on Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
analytical, fpga, hybrid algorithm, placement, simulated annealing | Simulated annealing,Hybrid algorithm,Computer science,Workload,Parallel computing,Field-programmable gate array,Real-time computing,Critical path delay,Speedup | Conference |
ISSN | ISBN | Citations |
1066-1395 | 978-1-4503-6252-8 | 0 |
PageRank | References | Authors |
0.34 | 0 | 8 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chengyu Hu | 1 | 132 | 28.60 |
| Qinghua Duan | 2 | 0 | 1.35 |
| Liran Hu | 3 | 0 | 0.34 |
| Peng Lu | 4 | 126 | 17.62 |
| Zhengjie Li | 5 | 1 | 2.73 |
| Meng Yang | 6 | 1028 | 55.17 |
| Wang Jian | 7 | 2 | 5.46 |
| Xu Hanyang | 8 | 5 | 9.57 |