Paper Info
Title
Characterizing Approximate Adders and Multipliers Optimized under Different Design Constraints
Abstract
Taking advantage of the error resilience in many applications as well as the perceptual limitations of humans, numerous approximate arithmetic circuits have been proposed that trade off accuracy for higher speed or lower power in emerging applications that exploit approximate computing. However, characterizing the various approximate designs for a specific application under certain performance constraints becomes a new challenge. In this paper, approximate adders and multipliers are evaluated and compared for a better understanding of their characteristics when the implementations are optimized for performance or power. Although simple truncation can effectively reduce the hardware of an arithmetic circuit, it is shown that some other designs perform better in speed, power and power-delay product. For instance, many approximate adders have a higher performance than a truncated adder. A truncated multiplier is faster but consumes a higher power than most approximate designs for achieving a similar mean error magnitude. The logarithmic multipliers are very fast and power-efficient at a lower accuracy. Approximate multipliers can also be generated by an automated process to be very efficient while ensuring a sufficiently high accuracy.
Year
DOI
Venue
2019
10.1145/3299874.3319454
Proceedings of the 2019 on Great Lakes Symposium on VLSI
Keywords
Field
DocType
adder, approximate computing, multiplier, power, speed
Truncation,Arithmetic circuits,Adder,Computer science,Algorithm,Mean squared error,Multiplier (economics),Electronic engineering,Exploit,Logarithm,Approximate computing
Conference
ISSN
ISBN
Citations 
1066-1395
978-1-4503-6252-8
1
PageRank 
References 
Authors
0.35
0
7
Name
Order
Citations
PageRank
Honglan Jiang11509.50
Francisco J. H. Santiago210.35
Mohammad Saeed Ansari3363.44
leibo liu4816116.95
Bruce F. Cockburn528734.39
Fabrizio Lombardi65710.81
Jie Han786366.92