Paper Info
Title
Optimization Of Pipelined Discrete Wavelet Packet Transform Based On An Efficient Transpose Form And An Advanced Functional Sharing Technique
Abstract
This paper presents an optimal implementation of a Daubechies-based pipelined discrete wavelet packet transform (DWPT) processor using finite impulse response (FIR) filter banks. The feed-forward pipelined (FFP) architecture is exploited for implementation of the DWPT on the field-programmable gate array (FPGA). The proposed DWPT is based on an efficient transpose form structure, thereby reducing its computational complexity by half of the system. Moreover, the efficiency of the design is further improved by using a canonical-signed digit-based binary expression (CSDBE) and advanced functional sharing (AFS) methods. In this work, the AFS technique is proposed to optimize the convolution of FIR filter banks for DWPT decomposition, which reduces the hardware resource utilization by not requiring any embedded digital signal processing (DSP) blocks. The proposed AFS and CSDBE-based DWPT system is embedded on the Virtex-7 FPGA board for testing. The proposed design is implemented as an intellectual property (IP) logic core that can easily be integrated into DSP systems for sub-band analysis. The achieved results conclude that the proposed method is very efficient in improving hardware resource utilization while maintaining accuracy of the result of DWPT.
Year
DOI
Venue
2019
10.3745/JIPS.01.0041
JOURNAL OF INFORMATION PROCESSING SYSTEMS
Keywords
Field
DocType
AFS Technique, CSDBE, Daubechies, DWPT, FIR Filter, FPGA, Pipelined Architecture
Transpose,Computer science,Field-programmable gate array,Real-time computing,Computational science,Finite impulse response,Discrete wavelet packet transform
Journal
Volume
Issue
ISSN
15
2
1976-913X
Citations 
PageRank 
References 
0
0.34
0
Authors
3
Name
Order
Citations
PageRank
Ngoc Hung Nguyen16311.10
Cheol Hong Kim27324.39
Jong-Myon Kim39125.99