Name
Title | ||
|---|---|---|
A high-efficiency good linearity 21 to 26.5 GHz fully integrated power amplifier using 0.18 μm CMOS technology |
Abstract | ||
|---|---|---|
This paper presents the design and implementation of a 21-26.5 GHz broadband, two stages CMOS power amplifier (PA) for quasi-millimeter wave band wireless communication systems. The proposed PA is designed using staggered tuning method [1], which is employed for the first time in quasi-millimeter wave band. Moreover, source and load-pull simulation, in addition to, impedance analysis are employed to optimize the input, output, and inter-stage impedance matching circuits for maximum power added efficiency (PAE) and better linearity. The measurement results on a chip fabricated using 0.18 mu m CMOS technology shows a power gain of 10.2 +/- 0.8 dB, a maximum PAE and output gain compression point (P-Out1dB) of 10.5 dBm and 18 %, respectively, at 24 GHz while consuming 42 mW only. In addition, the PA achieved excellent low measured group delay variations of 75 +/- 22 ps. |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/MWSCAS.2016.7870065 | Midwest Symposium on Circuits and Systems Conference Proceedings |
Keywords | Field | DocType |
Power Amplifier (PA),Power Added Efficiency (PAE) | Power gain,Computer science,Linearity,Impedance matching,Electronic engineering,CMOS,Staggered tuning,RF power amplifier,Gain compression,Amplifier | Conference |
ISSN | Citations | PageRank |
1548-3746 | 0 | 0.34 |
References | Authors | |
0 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mosalam, H. | 1 | 2 | 1.73 |
| Allam, A. | 2 | 2 | 7.12 |
| Adel Abdelrahman | 3 | 6 | 5.14 |
| Takana Kaho | 4 | 11 | 5.35 |
| Hongting Jia | 5 | 2 | 4.32 |
| R. K. Pokharel | 6 | 9 | 8.47 |