Name
Title | ||
|---|---|---|
A 3.5–6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH $Delta Sigma $ -TDC for Low In-Band Phase Noise |
Abstract | ||
|---|---|---|
This paper proposes a digital-to-time converter (DTC)-assisted fractional-N wide-bandwidth all-digital phaselocked loop (ADPLL) with a fine-resolution time-to-digital converter (TDC). The TDC employs a two-channel time-interleaved time-domain register with an implicit adder/subtractor realizing an error-feedback topology. Such an error-feedback unit of a first-order ΔΣ-TDC can be cascaded as a mul... |
Year | DOI | Venue |
|---|---|---|
2016 | 10.1109/JSSC.2017.2682841 | IEEE Journal of Solid-State Circuits |
Keywords | Field | DocType |
Phase locked loops,Clocks,Oscillators,Frequency conversion,Bandwidth,Frequency modulation,Quantization (signal) | Phase-locked loop,Digitally controlled oscillator,Subtractor,Computer science,Control theory,Phase noise,Electronic engineering,Delta-sigma modulation,CMOS,Noise shaping,Jitter | Conference |
Volume | Issue | ISSN |
52 | 7 | 0018-9200 |
Citations | PageRank | References |
8 | 0.57 | 27 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ying Wu | 1 | 8 | 0.57 |
| Mina Shahmohammadi | 2 | 95 | 8.84 |
| Yue Chen | 3 | 150 | 39.62 |
| Ping Lu | 4 | 10 | 1.28 |
| Robert Bogdan Staszewski | 5 | 536 | 93.76 |